1. Field of the Invention
The present invention relates to an eDRAM-type semiconductor device including a logic circuit section and an embedded dynamic random access memory (eDRAM) section which are incorporated in one semiconductor substrate, and also relates to a method for manufacturing such an eDRAM-type semiconductor device.
2. Description of the Related Art
In a prior art process of manufacturing a plurality of eDRAM-type semiconductor devices, a semiconductor wafer such as a silicon wafer is prepared, and a surface of the semiconductor wafer is sectioned into a plurality of semiconductor chip areas which are defined by grid-like scribe line areas on the semiconductor wafer. The eDRAM-type semiconductor device includes a logic circuit section and a DRAM section, which are incorporated in one semiconductor substrate defining a semiconductor chip area.
The DRAM memory section includes a memory cell array in which a plurality of memory cells are formed, and each of the memory cells is composed of a metal oxide semiconductor (MOS) transistor or so-called cell transistor, and a capacitor associated therewith. In order to enhance the integration of the DRAM memory section, it is necessary to form the capacitor as small as possible. However, in order to ensure a given retention time in the DRAM memory section, the capacitor must have a certain capacitance. Namely, the opposed electrodes of the capacitor must have an area necessary to ensure the retention time.
For this reason, the capacitor is incorporated in a small hole formed in an insulating layer. In particular, a metal layer is formed on a surface of the insulating layer such that the hole is traversed with the metal layer. Then, a photoresist resin layer is formed on a surface of the insulating layer on the metal layer, and a portion of the metal layer which is formed on the surface of the insulating layer is removed by using a photolithography and etching process. Namely, the other portion of the metal layer which is formed on the inner wall face of the hole remains as a lower electrode of the capacitor.
The aforesaid photolithography and etching process involves an exposure process in which only the portion of the metal layer, formed on the surface of the insulating layer, is exposed with a light ray, such as an i-ray, a KrF-ray, an ArF-ray or the like. Namely, the other portion of the metal layer formed on the inner wall face of the hole is not exposed with the light ray. Nevertheless, in this prior art exposure process, no mask for masking the hole is used, because a diameter of the hole and an exposure time for the light ray are previously selected in accordance with a wavelength of the light ray to be used, so that the photoresist resin materials, with which the hole is stuffed, are not exposed with the light ray.
Note, in the prior art exposure process, a mask is merely used for exposing only one of the semiconductor chip areas on the semiconductor wafer with the light ray.